View MAX9312_4702701.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-2079; Rev 2; 4/09
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
General Description
The MAX9312/MAX9314 are low skew, dual 1-to-5 differential drivers designed for clock and data distribution. These devices accept two inputs. Each input is reproduced at five differential outputs. The differential inputs can be adapted to accept single-ended inputs by connecting the on-chip VBB supply to one input as a reference voltage. The MAX9312/MAX9314 feature low part-to-part skew (30ps) and output-to-output skew (12ps), making them ideal for clock and data distribution across a backplane or a board. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The MAX9312 features an on-chip VBB reference output of 1.425V below the positive supply voltage. The MAX9314 offers an on-chip VBB reference output of 1.32V below the positive supply voltage. Both devices are offered in an industry-standard 32-pin 7mm x 7mm LQFP package. In addition, the MAX9312 is offered in a space-saving 32-pin 5mm x 5mm TQFN package.
Features
o +2.25V to +3.8V Differential HSTL/LVPECL Operation o -2.25V to -3.8V Differential LVECL Operation o 30ps (typ) Part-to-Part Skew o 12ps (typ) Output-to-Output Skew o 312ps (typ) Propagation Delay o 300mV Differential Output at 3GHz o On-Chip Reference for Single-Ended Inputs o Output Low with Open Input o Pin Compatible with MC100LVEP210 (MAX9312) and MC100EP210 (MAX9314) o Offered in Tiny QFN* Package (70% Smaller Footprint than LQFP)
MAX9312/MAX9314
Ordering Information
PART MAX9312ECJ+ MAX9312ETJ+ MAX9314ECJ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 32 LQFP 32 TQFN-EP* 32 LQFP
Applications
Precision Clock Distribution Low-Jitter Data Repeater
*Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package.
Functional Diagram
QA0 VCC VCC QA0 QA1 QA1 QA2 QA2 75k 75k QA3 VEE VBB VEE QA3 QA4 QA4 VEE VEE CLKB CLKB 75k 75k QB3 QB3 QB4 QB4 75k QB0 QB0 QB1 QB1 QB2 QB2
75k CLKA CLKA
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9312/MAX9314
ABSOLUTE MAXIMUM RATINGS
VCC - VEE...............................................................................4.1V Inputs (CLK_, CLK_) .............................VEE - 0.3V to VCC + 0.3V CLK_ to CLK_ ....................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB Sink/Source Current ...............................................0.65mA Continuous Power Dissipation (TA = +70C) 32-Pin LQFP (derate 20.7mW/C above +70C) ....1652.9mW 32-Pin TQFN (derate 34.5mW/C above +70C)....2758.6mW Junction-to-Case Thermal Resistance (TJC) (Note A) 32-Pin LQFP ................................................................12C/W 32-Pin TQFN ..................................................................2C/W Junction-to-Ambient Thermal Resistance (TJA) (Note 1) 32-Pin LQFP .............................................................48.4C/W 32-Pin TQFN ................................................................29C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (CLK_, CLK_, Q_, Q_) ........................2kV Soldering Temperature (10s) ...........................................+300C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V.) (Notes 2-5)
PARAMETER SYMBOL CONDITIONS -40C MIN MAX MIN +25C MAX MIN +85C MAX UNITS
INPUTS (CLK_, CLK_) VBB connected MAX9312 to CLK_ (VIL for VBB connected MAX9314 to CLK_) VBB connected MAX9312 to CLK_ (VIL for VBB connected MAX9314 to CLK_) VCC 1.23 VCC 1.165 VCC VCC 1.23 VCC 1.165 VCC VCC 1.23 VCC 1.165 VCC V VCC VCC VCC
Single-Ended Input High Voltage
VIH
Single-Ended Input Low Voltage
VEE
VCC 1.62 VCC 1.475 VCC VCC 0.095 VCC VEE 3.0 150
VEE
VCC 1.62 VCC 1.475 VCC VCC 0.095 VCC VEE 3.0 150
VEE
VCC 1.62 V VCC 1.475 VCC VCC 0.095 VCC VEE 3.0 150 A A V V
VIL
VEE VEE + 1.2 VEE
VEE VEE + 1.2 VEE 0.095 0.095
VEE VEE + 1.2 VEE 0.095 0.095
High Voltage of Differential Input Low Voltage of Differential Input Differential Input Voltage Input High Current CLK_ Input Low Current
VIHD VILD VIHD VILD IIH IILCLK For VCC - VEE < 3.0V For VCC - VEE 3.0V
0.095 0.095
V
-10
+10
-10
+10
-10
+10
2
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V.) (Notes 2-5)
PARAMETER CLK_ Input Low Current SYMBOL IILCLK CONDITIONS -40C MIN -150 MAX MIN -150 +25C MAX MIN -150 +85C MAX UNITS A
MAX9312/MAX9314
OUTPUTS (Q__, Q__) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage VOH Figure 1 VCC 1.025 VCC 0.900 VCC 1.025 VCC 0.900 VCC 1.025 VCC 0.900 V
VOL VOH VOL
Figure 1
VCC -1.930 670
VCC 1.695 950
VCC -1.930 670
VCC 1.695 950
VCC -1.930 670
VCC 1.695 950
V
Figure 1
mV
REFERENCE (VBB) Reference Voltage Output (Note 6) POWER SUPPLY Supply Current (Note 7) MAX9312 VBB IBB = 0.5mA MAX9314 VCC 1.525 VCC 1.38 VCC 1.325 VCC 1.26 VCC 1.525 VCC 1.38 VCC 1.325 VCC 1.26 VCC 1.525 VCC 1.38 VCC 1.325 V VCC 1.26
IEE
75
82
95
mA
_______________________________________________________________________________________
3
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9312/MAX9314
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE, unless otherwise noted. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V.) (Note 8)
PARAMETER Differential Inputto-Output Delay Output-to-Output Skew (Note 9) Part-to-Part Skew (Note 10) Added Random Jitter (Note 11) Added Deterministic Jitter (Note 11) SYMBOL tPLHD, tPHLD tSKOO tSKPP fIN = 1.5GHz clock pattern fIN = 3.0GHz clock pattern 3Gbps, 223 -1 PRBS pattern VOH - VOL 300mV, clock pattern, Figure 2 fMAX VOH - VOL 500mV, clock pattern, Figure 2 Figure 2 1.5 100 112 140 CONDITIONS Figure 2 -40C MIN 220 TYP 321 12 30 1.2 1.2 MAX 380 46 160 2.5 2.6 MIN 220 +25C TYP 312 12 30 1.2 1.2 MAX 410 46 190 2.5 2.6 MIN 260 +85C TYP 322 10 30 1.2 1.2 MAX 400 35 140 2.5 2.6 UNITS ps ps ps
tRJ
ps (RMS)
tDJ
80
95
80
95
80
95
ps (pk-pk)
3.0 1.5 100
3.0 1.5 116 140 100
3.0 GHz
Switching Frequency
Output Rise/Fall Time (20% to 80%)
tR, tF
121
140
ps
Note 2: Measurements are made with the device in thermal equilibrium. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 4: Single-ended input operation using VBB is limited to VCC - VEE = 3.0V to 3.8V for the MAX9312 and VCC - VEE = 2.7V to 3.8V for the MAX9314. Note 5: DC parameters production tested at TA = +25C. Guaranteed by design and characterization over the full operating temperature range. Note 6: Use VBB only for inputs that are on the same device as the VBB reference. Note 7: All pins open except VCC and VEE. Note 8: Guaranteed by design and characterization limits are set at 6 sigma. Note 9: Measured between outputs on the same part at the signal crossing points for a same-edge transition. Note 10: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 11: Device jitter added to the input signal.
4
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9312/MAX9314
Typical Operating Characteristics
(VCC = +3.3V, VEE = 0, VIHD = VCC - 0.95V, VILD = VCL - 1.25V, input transition time = 125ps (20% to 80%), fIN = 1.5GHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT, IEE vs. TEMPERATURE
MAX9312 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9312 toc02
TRANSITION TIME vs. TEMPERATURE
tR 125 TRANSITION TIME (ps) 120 115 110 105 100 95 90 tF
MAX9312 toc03
80 75 SUPPLY CURRENT (mA) 70 65 60 55
0.9 0.8 OUTPUT AMPLITUDE (V) 0.7 0.6 0.5 0.4 0.3 0.2 0.1
130
50 -40
0 -15 10 35 60 85 0 1000 2000 3000 TEMPERATURE (C) FREQUENCY (MHz)
-40
-15
10
35
60
85
TEMPERATURE (C)
MAX9312 toc04
304 PROPAGATION DELAY (ps) 302 300 298 296 294 292 290 288 1.0 1.4 1.8 2.2 tPHLD tPLHD
VIHD -VILD = 150mV
VIHD = VCC - 0.95V VILD = VCC - 1.1V PROPAGATION DELAY (ps)
320 tPLHD 300 tPHLD
280 2.6 3.0 3.4 3.8 -40 -15 10 35 60 85 VIHD (V) TEMPERATURE (C)
_______________________________________________________________________________________
MAX9312 toc05
306
PROPAGATION DELAY vs. SINGLE-ENDED HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
PROPAGATION DELAY vs. TEMPERATURE
340
5
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9312/MAX9314
Pin Description
PIN 1, 9, 16, 25, 32 2 3 4 5 6 7 8 10 11 12 13 14 15 17 18 19 20 21 22 23 24 26 27 28 29 30 31 -- NAME VCC N.C. CLKA CLKA VBB CLKB CLKB VEE QB4 QB4 QB3 QB3 QB2 QB2 QB1 QB1 QB0 QB0 QA4 QA4 QA3 QA3 QA2 QA2 QA1 QA1 QA0 QA0 EP FUNCTION Positive Supply Voltage. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. No Connection. Internally not connected. Noninverting Differential Clock Input A Inverting Differential Clock Input A Reference Output Voltage. Connect to the inverting or noninverting clock input to provide a reference for single-ended operation. When used, bypass to VCC with a 0.01F ceramic capacitor. Noninverting Differential Clock Input B Inverting Differential Clock Input B Negative Supply Voltage Inverting QB4 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB4 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QB3 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB3 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QB2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QB1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QB0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QB0 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QA4 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QA4 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QA3 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QA3 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QA2 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QA2 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QA1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QA1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting QA0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting QA0 Output. Typically terminate with 50 resistor to VCC - 2V. Exposed Pad (TQFN package only). Internally connected to VEE. Connect EP to the VEE pad on the PCB.
6
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Detailed Description
The MAX9312/MAX9314 are low-skew, dual 1-to-5 differential drivers designed for clock and data distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The differential inputs can be configured to accept single-ended inputs when operating at approximately VCC VEE = 3.0V to 3.8V for the MAX9312 or VCC - VEE = 2.7V to 3.8V for the MAX9314. This is accomplished by connecting the on-chip reference voltage, VBB, to an input as a reference. For example, the differential CLKA, CLKA input is converted to a noninverting, single-ended input by connecting VBB to CLKA and connecting the singleended input to CLKA. Similarly, an inverting input is obtained by connecting VBB to CLKA and connecting the single-ended input to CLKA. With a differential input configured as single ended (using VBB), the singleended input can be driven to VCC and VEE or with a single-ended LVPECL/LVECL signal. When a differential input is configured as a single-ended input (using VBB), the approximate supply range is VCC VEE = 3.0V to 3.8V for the MAX9312 and VCC - VEE = 2.7V to 3.8V for the MAX9314. This is because one of the inputs must be VEE + 1.2V or higher for proper operation of the input stage. VBB must be at least VEE + 1.2V because it becomes the high-level input when the other (single-ended) input swings below it. Therefore, minimum VBB = VEE + 1.2V. The minimum V BB output for the MAX9312 is V CC 1.525V and the minimum VBB output for the MAX9314 is VCC - 1.38V. Substituting the minimum VBB output for each device into VBB = VEE + 1.2V results in a minimum supply of 2.725V for the MAX9312 and 2.58V for the MAX9314. Rounding up to standard supplies gives the single-ended operating supply ranges of VCC - VEE = 3.0V to 3.8V for the MAX9312 and VCC - VEE = 2.7V to 3.8V for the MAX9314. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If the VBB reference is not used, it can be left open. The VBB reference can source or sink 0.5mA, which is sufficient to drive two inputs. Use VBB only for inputs that are on the same device as the VBB reference. The maximum magnitude of the differential input from CLK_ to CLK_ is 3.0V or VCC - VEE, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting inputs (CLKA and CLKB) are biased with a 75k pullup to VCC and a 75k pulldown to VEE. The noninverting inputs (CLKA and CLKB) are biased with a 75k pulldown to VEE. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD). Output levels are referenced to VCC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are LVPECL. The outputs are LVECL when VCC is connected to GND and VEE is connected to a negative supply. A single-ended input of at least VBB 95mV or a differential input of at least 95mV switches the outputs to the V OH and V OL levels specified in the DC Electrical Characteristics table.
MAX9312/MAX9314
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F value capacitor closest to the device. Use multiple parallel vias for low inductance. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC (if the VBB reference is not used, it can be left open).
Traces
Input and output trace characteristics affect the performance of the MAX9312/MAX9314. Connect each signal of a differential input or output to a 50 characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces.
Output Termination
Terminate outputs through 50 to VCC - 2V or use an equivalent Thevenin termination. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if QA0 is used as a single-ended output, terminate both QA0 and QA0.
_______________________________________________________________________________________
7
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9312/MAX9314
CLK_ VIH CLK_ VIL VBB (CONNECTED TO CLK_) VOH VOH - VOL Q_ VOL
Q_
Figure 1. Switching with Single-Ended Input
CLK_ VIHD - VILD CLK_ tPLHD Q_ VOH - VOL Q_ tPHLD
VIHD VILD
VOH VOL
80% 0 (DIFFERENTIAL) (Q_) - (Q_) 20% tR
80% 0 (DIFFERENTIAL) 20% tF
Figure 2. Differential Transition Time and Propagation Delay Timing Diagram
Pin Configuration
PROCESS: BIPOLAR
TOP VIEW
VCC QA0 QA0 QA1 QA1 QA2 QA2 VCC 32 31 30 29 28 27 26 25
Chip Information
VCC N.C. CLKA CLKA VBB CLKB CLKB VEE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
24 QA3 23 QA3 22 QA4 21 QA4
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 32 LQFP 12 TQFN-EP PACKAGE CODE C32-1 T3255+4 DOCUMENT NO. 21-0054 21-0140
MAX9312 MAX9314
20 QB0 19 QB0 18 QB1 17 QB1
VCC QB4 QB4 QB3 QB3 QB2 QB2 VCC
LQFP OR TDFN
8
_______________________________________________________________________________________
Dual 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Revision History
REVISION NUMBER 2 REVISION DATE 4/09 DESCRIPTION Added lead-free TQFN package for MAX9312, deleted future product packages for MAX9314, and updated Pin Description PAGES CHANGED 1, 6
MAX9312/MAX9314
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

▲Up To Search▲

Price & Availability of MAX9312

	To Download MAX9312 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .